EE 201A/EE201B

Modeling and Optimization for VLSI Layout

2004 Spring

Time:12:00 - 1:50 TR
Place: 5436 Boulter

Instructor: Lei He
Department of Electrical Engineering
Office: 62037 Engineering IV
Phone: 206 2037

Course Outline and Schedule

Front-end physical design (4.5 weeks) Back-end physical design (4.5 weeks)

Grading Policy:
15% homework, 20% midterm, 15% presentation, and 50% project.

Student Presentation:

Course Project:

Programming Homework: 3D packing
Lecture Notes
Chapter 1: Introduction ppt

Chapter 2: Partitioning and clustering ppt
Reading: Student presentation: Multilevel Hypergraph Partitioning Chapter 3: Floorplanning ppt
Reading: Student presentation: Non-slicing floorplanning (ppt). Chapter 4: placement ppt
Reading: Student presentation: analytical-based placement (ppt). Chapter 5: Power and Thermal Modeling
Sudent presentation: Reading: Chapter 6: Interconnect RC and RLC modeling ppt1 ppt2
Reading: Chapter 7: Interconnect delay delay moment
Chapter 8: Student presentations
Chapter 9: transistor sizing and circuit tuning ppt
Reading: Chapter 10: Buffering and FF insertion
PPT: lecture and student presentation
Chapter 11: noise aware routing
Overview: lecture
Reading: Student presentation on multi-level routing
Reading: Student presentation on noise model
Reading: Chapter 12: Review and take home exam
review and exam