PTscalar is a cycle-accurate microarchitecture-level performance and power simulator for SuperScalar architectures. It is based on the microarchitecture-level performance simulator Simplescalar and a few parameterized power models. PTscalar reads the user specified power parameters and system configuration, then computes performance and power statistics for each functional unit and the whole system in every clock cycle. PTscalar can be used to evaluate software and compiler optimization, microarchitecture innovation, and software and hardware co-design/tradeoff for performance and power optimization. PTsclar includes the temperature dependent leakage power model and built-in thermal model considering three dimensional heat transfer and packages such as heat spreader and heat sink. PTscalar is capable of thermal and transient-current estimations as well as coupled power and thermal simulation considering the dependence between leakage power and temperature.
This research was partially supported by the NSF CAREER award CCR-0306682, SRC grant 2000-HJ-782, SRC grant HJ-1008, a UC MICRO grant sponsored by Analog Devices, Fujitsu Laboratories of America, Intel and LSI Logic, and a Fraulty Partner Award by IBM. We used computers donated by Intel and SUN Microsystems. We developed PTscalar based on Simplescalar toolset. Address comments to Professor Lei He.