SINO/SPR: SIGNAL AND POWER NET SYNTHESIS UNDER RLC MODEL

Project director: Lei He
Authors: Kevin Lepak , James Ma , Irwan Luwandi, and Min Xu
 

VLSI Design and Design Automation Laboratory
Department of Electrical and Computer Engineering
University of Wisconsin - Madison

Introduction:

SINO/SPR is an interconnect synthesis tool for capacitive and inductive noise minimization. It is developed at UW EDA Lab and contains:
     (1) min-area simultaneous shield insertion and net ordering (SINO);
     (2) formula-based interconnect area estimation for optimal SINO solutions;
     (3) min-area simultaneous signal and power routing (SPR).
Efficient algorithms have been implemented with SPICE netlist generation under RC and RLC model.


Presentation at Design Automation Conference 2001 - University Booth

Reference:

(1) K. M. Lepak, I. Luwandi, and L. He, "Shield insertion and net ordering under explicit RLC noise constraint", Design Automation Conference, June 2001. (pdf)
(2) J. D. Ma and L. He, "Simultaneous Signal and Power Routing Based on Keff Model,'' ACM International Workshop on System-Level Interconnect Prediction, April 2001. (pdf)
(3) L. He and K. M. Lepak, "Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization", IEEE/ACM International Symposium on Physical Design, April 2000 (pdf) (presentation)

Interconnect Synthesis Tool of EDA@WISC. Address comments to lhe@ece.wisc.edu or dma@students.wisc.edu