Interconnect Modeling and Design with RLC Crosstalk Constraints

Advisor: Prof. Lei He (lhe@ee.ucla.edu)

Students: Jinjun Xiong (jinjun@ee.ucla.edu) Jun Chen (junc@cae.wisc.edu) Hao Yu (hy255@ee.ucla.edu)

Design Automation Lab, Electrical Engineering Department,

University of California at Los Angeles

Abstracts:

Signal integrity becomes one of primary design constraints as the clock frequency increases and minimum feature size continues to shrink. State-of-the-art noise avoidance techniques use only a capacitive model. However, inductive coupling gains growing importance for GHz+ VLSI design. We present the following for RLC interconnect modeling and design:

(1) RLC noise modeling at both tile and full-chip levels;

(2) Tile-based interconnect synthesis and chip-level post-routing optimization, both under RLC crosstalk constraints;

(3) Chip-level global routing synthesis and optimization with RLC crosstalk constraints.

　

Related Packages:

TRIO2: Interconnect modeling and extracting package


GSINO: Extended global router that synthesizes a global routing solution without RLC crosstalk violation

WebHenry: Web-based interconnect inductance extraction


VPEC: Provable passive and cost efficient interconnect inductance modeling