Yan Lin 8/15/05
week 32

* TCAD revision II.
   1) Finished SPICE simulation for LCs with power-gating
	- 8% delay overhead compared to w/o power-gating
        - 7% chip level area overhead (151% -> 158%)
   2) Fixed bug in Psim
        _ Leakage power of LCs for connection switches is double counted
        - Re-run experiments for fine-grained LC insertion
   3) Re-run LP based algorithm for clma
        - Program can be finished in 15H now!!
            - Due to updated objective function considering leakage?
            - Due to updated Linux operation system?
        - For relaxed time spec., program is still running.
   4) Finished coding for alternative approaches for greedy dual-Vdd tree based assignment
        - First assign interconnects then CLBs
        - Uniformly assign interconnects and CLBs
        - Experiments are running