In the past week, I was working on the followings.

- Discussed with Yu on cleaning up the bottom-up assignment code. 
  Suggested him to comment out some debug and robustic code which 
  is only useful when error happens.

- Enhanced original vpr_lp to coonsider multiple buffer sizes
  -- enhanced the architecture format such that buffer size is specified in
     the arch file instead of hard-coded in code
  -- enhanced the original physical netlist dumper considering multiple buffer
     sizes

- Finished the coding on dTLC-LP for mixed wire lengths.
  -- moved the remained hard-coded capacitance value into aux_cap.lib
  -- moved the low-vdd buffer resistance, delay, leakage and dynamic energy
     into dual_vdd.lib
  -- finished coding on dTLC-LP for mixed wire lengths

- Reviewed TCAD paper "Device-Aware Yield-Centric Dual-Vdd and Transistor
  Sizing Under Process Parameter Variations".

Ongoing work includes

- Debug and test extended dTLC-LP
- Coding on time slack allocation considering process variations.