In the last week, I was working on the follows,

Extended dTLC-LP algorithm
- Enhanced the algorithm to evaluate 
  - estimated vddl switch number, leakage and dynamic power reduction
  - leakage and dynamic power reduction before and after refinement
  - leakage and dynamic power consumption after refinement
- Evaluated EdTLC-LP in 100nm technology using 20 MCNC designs

Process Variation Project
- Implemented library file interface for process variation projects
- Enhanced the timing analyzer in VPR to take delay variation into account
- Finished coding on robustic linear programming, time yield only
  - Both worst case and time-yield constraint versions are finished
- Finished coding on bottom-up assignment and global refinement considering
  delay variation
  - Found an error in my rlp_slack.pdf, correlation is NOT taken into
    account in the written part on bottom-up assignment and global refinement
- Ongoing work includes
  - Debugging and testing the robustic LP formulation considering delay
    variations
  - Coding on SOCP considering both delay and power variation

Miscellaneous
- Proof-read TVLSI final version and submitted it.
- Discussed with Yu on vddl switch number estimation and sampling etc.
- Discussed with Lijuan on low-power FPGA project