In the last week, I was working on the followings,
- ARR poster on stochastic physical synthesis
- working with Fei for revision of TCAD paper on Vdd-programmable FPGAs
- DAC06 final version (with Yu)
- paper reading
    * "Voltage scheduling under unpredictability: A risk management paradigm", A. Davoodi and A.Srivastava from Maryland;
        Comments: The uncertainty is from inaccuracy on power/delay when performing high-level voltage scheduling but not power noise.
        The risk is defined as the case in which the expected clock period cannot be achieved. The problem formulation is to assign the voltage
        level to each operation node and the risk is minimized. The uncertainty in power and delay is modeled by assuming Voltage supply is
        a Gaussian in the problem formulation and also in the evaluation stage. I don't think this verification is sophisticated and valid in general.
    * continue read paper on technology mapping such as EMap, CutMap etc. (link)