In the last week, I was working on the followings,
- paper reading
* "Optimal simultaneous mapping and clustering for FPGA delay optimization", Y. Lin, D. Chen and J. Cong, DAC'06
This paper performs simultaneous mapping and clustering to improve timing. The algorithm consists of two stages similar to technology mapping. In the first stage, the optimal arrival time in a mapped and clustered solution for each node is calculated. LUT and cluster cuts are enumerated simultaneously in a recursive fashion. In the second stage, cuts for LUT and cluster are selected for each node under timing and area constraint. Several heuristics are used as a post clustering procedure to reduce the large area (cluster) overhead.
The downsides and limitations are as follows:
i) large area (cluster number) overhead, 22% with all heuristics and more than 100% by the proposed algorithm alone.
ii) required routing channels are not presented
iii) as mentioned by the authors, cluster input constraint is not considered
iv) timing optimality is only valid for LUT duplication free case
v) 100X runtime overhead compared to DAOMap + T-VPack
vi) Timing improvement is achieved by algorithm + post heuristics, not clear about the timing with proposed algorithm alone

* [1] J. Cong and S. Xu, "Delay-optimal technology mapping for FPGAs with heterogeneous LUTs", DAC'98
   [2] -, "Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources", ICCAD'98
[1] minimize delay with unbounded resources for each type of LUT. It is a simple extension from FlowMap with cut generation with different cut sizes. [2] extends [1] for the problem with bounded resources for each type of LUT. Optimal solution can be achieved for tree while it is proved that delay optimal mapping is NP-hard for DAG when K > 4, where K is the minimum LUT size. Two heuristics leverage mapping in [1] based on binary search on delay to find a valid solution that satisfiy resource constraint are presented.

- paper review on recent publications on statistical gate sizing (link)
- helped Lerong on device and architecture co-optimization journal