Index of /member_only/FPGA/fault_tol_fpga/vik_2005_0919_papers_survey/Lemieux_Papers

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]1_lemieux_defect_tol_impact_of_gran.pdf2023-03-29 08:29 170K 
[ ]lemieux_HW_perf_mon_in_MP_MS_thesis.pdf2023-03-29 08:29 214K 
[ ]lemieux_NUMAchineTechnicalReport.ps2023-03-29 08:29 451K 
[ ]lemieux_NUMAchine_HW_ref_maint_manual.pdf2023-03-29 08:29 617K 
[ ]lemieux_NUMAchine_global_ring_HW_design.pdf2023-03-29 08:29 198K 
[ ]lemieux_NUMAchine_multiprocessor.pdf2023-03-29 08:29 109K 
[ ]lemieux_NUMAchine_multiprocessor.ppt2023-03-29 08:29 3.8M 
[ ]lemieux_NUMAchine_sys_prog_manual.pdf2023-03-29 08:29 248K 
[ ]lemieux_anal_framework_switch_block_design.pdf2023-03-29 08:29 148K 
[ ]lemieux_circ_design_fpga_routing_switches.pdf2023-03-29 08:29 137K 
[ ]lemieux_defect_tol_fpga_switch_block_conn_block.pdf2023-03-29 08:29 315K 
[ ]lemieux_design_implem_NUMAchine_multiproc.pdf2023-03-29 08:29 40K 
[ ]lemieux_designing_for_highspeed_perf_CPLD_FPGA.pdf2023-03-29 08:29 30K 
[ ]lemieux_detailed_router_allocating_wire_seg_FPGAs.pdf2023-03-29 08:29 47K 
[ ]lemieux_dir_and_single_driver_wires_fpga_interc.pdf2023-03-29 08:29 358K 
[ ]lemieux_dsign_implem_router_SW_seg_arch_FPGA_BS_thesis.pdf2023-03-29 08:29 280K 
[ ]lemieux_generating_highly_routable_sparse_crossbars_PLDs.pdf2023-03-29 08:29 187K 
[ ]lemieux_logic_block_cluster_chan_width_cons_fpga.pdf2023-03-29 08:29 295K 
[ ]lemieux_overview_NUMAchine_multiproc_proj.pdf2023-03-29 08:29 189K 
[ ]lemieux_poster_checkerboard_switch_block_topo_rout_div.pdf2023-03-29 08:29 174K 
[ ]lemieux_seg_routing_speed_perf_rout_fpga.pdf2023-03-29 08:29 83K 
[ ]lemieux_two_step_routing_for_FPGAs.pdf2023-03-29 08:29 106K 
[ ]lemieux_using_sparse_crossbars_LUT_clusters.pdf2023-03-29 08:29 124K 
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