09-17-07 to 09-23-07

I've finished the implementation of the framework for the re-synthesis platform.
The implementation is built on OpenAccess system, which is a popular platform 
for industrial interfaced ICCAD software. My implementation includes the 
following parts:

1. A LUT mapper (read in a circuit described by OA format, and map it to LUTs)
2. A graph (resynthesis graph) representation for the LUT-mapped circuit, 
where the combinational part of the circuit is extracted
3. Cone (both SIMO and MIMO) generations in the resynthesis graph.
4. A simulator to compute the cone's logic function
5. A re-synthesis framework to greedily re-synthesize the circuit, 
i.e., generate a cone, test the feasibility and re-synthesize it if 
it's feasible to the library PLBs.
6. A plot tool to visualize the re-synthesis graph.

I've copied the code in Victor's home directory in our server, 
"/home/vshih/oa/OAGear-0.97a/Resynthesis". 
Victor will integrate your Boolean matcher implementation in the feasibility 
test (part 5) in my code. To run my code, go to "testing" sub-directory 
and type " rs.sh s27" (run test case "s27", the smallest circuit in 
the benchmark set). After running, one will see the log file deposited in 
"rs_log/s27.log" and a postscript file in "rs_plot/s27.ps". 
One can see the graph in this ps file.