BruinSyn: UCLA FPGA RTL Synthesizer

0.97a

Version: 0.1

Copyright

(c) Copyright University of California Los Angeles. All rights reserved.

Introduction

BruinSyn package perform the RTL synthesis on Verilog with behavioral descriptions and generate a structural Verilog which maps the original design to a specific FPGA family.

The following is the project reports which are updated timely during the development of the whole system.

• Current System Partition
• Current Progress (Section Current Progress)

The rest of this documentation is as follows.

• Organization of this package (Section Organization of the Package)
• Compilation of this package (Section Compilation Guide)
• Visualization and Debug (Section Verilog Writer and Visualization)
• General suggestions and tips for developer in OAGear (Section General Suggestions for Coding in OAGear)

For the overal design documentation and more reference, please take a look at the here or following web site http://www.ee.ucla.edu/~hu/bruin_syn_docs/design/, with user/passwd as "yuhu/uclasynthesis".

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