VPR / NANO TASK TIMELINE
Vikram Rao and Sasank Reddy

A. Major Tasks to be Completed:

1. Learn VPR: 

	i) run existing files through flow (existing .arch files)

	ii) learn .arch file structure

	iii) create a basic FPGA model

2. Start modeling nanoFPGA:

	i) develop model for FPGA architecture with litho wires, molecular switches (based on Penn State models used in "Exploring Technology Alternatives for Nano-Scale FPGA Interconnects")

	ii) write .arch file for FPGA with: litho wires, molecular switches (based on Penn State work)

3. Modify routing for defective molecular switches:

	i) modify VPR routing for FPGA with: perfect litho wires, imperfect (defective) molecular switches using modified version of DeHon's algorithm in "Greedy Algorithm for Tolerating Defective Crosspoints in NanoPLA Design" to work with FPGAs instead of PLAs. 
		- (Must modify VPR to read in molecular switch defect map of FPGA, then route around defective switches using DeHon's algorithm)	
		- QUESTION: What are the differences in applying this algorithm to ROUTING in FPGAs?
		a) model imperfect (defective) molecular switches in switch block
		b) model imperfect (defective) molecular switches in connection block
		c) model imperfect (defective) molecular switches in both switchblock and connection block

4. Develop fault-tolerant approach using redundant molecular switches and formula for number of redundant molecular switches required to attain desired routability percentage 

5. Aqcuire area overhead, critical path delay estimates using MCNC benchmarks

6. Continue modeling nanoFPGA:

	i) develop model for FPGA architecture with nano wires, molecular switches (based on Penn State models used in "Exploring Technology Alternatives for Nano-Scale FPGA Interconnects")

	ii) write .arch file for FPGA with: nano wires, molecular switches (based on Penn State work)

7. Modify model and routing for FPGA described in (1-4) to add modeling / routing of FPGA with defective nano wires:

	i) modify VPR modeling / routing for FPGA with: imperfect (defective) nano wires using stochastic assembly as described in Dehon's work "Stochastic Assembly of Sublithographic Nanoscale Interfaces" (use modulation doping to address individual nanowires, self-assembly to organize them into nanoscale-pitch decoder arrays)

8. Acquire area overhead, critical path delay estimates using MCNC benchmarks

B. Timeline for Tasks Described Above:

12/4/05 - 12/11/05- Complete Tasks #1,2

12/11/05 - 12/19/05- Work on Task #3		
	
12/19/05- Checkpoint on Task #3, work on Task #3 will likely continue in Winter Quarter, 2006

1/6/06- Winter Quarter Begins; Assess Progress to set further deadlines