Yan Lin, weekly report, 5/15/05

1) TCAD paper revision
i) I implemented the assignment algorithm presented in "A Dual-Vdd Low Power
FPGA Architecture", A. Gayasen et al, FPL'04. The level converters are inserted
at CLB inputs. All elements are assigned to VddH originally. All the nets driven
by one CLB will have the same Vdd-level as the source CLB.

ii) I was working on the experiments. Vdd-level assignment for fine-grained LC 
inserted, tree-based, segment-based, LP-based and penn state's approach are 
almost finished for no relaxed Tspec and relaxed Tspec cases. The ongoing work 
includes setting up power simulation and collecting data. 

iii) Spice simulation was performed to show that the Vdd-level has little
impact on load capacitance and input capacitance. The result is shown as below
for a 7X buffer,

Vdd	C_in	C_out
1.3v	2.3fF	9.8fF
0.8v	2.2fF	10.2fF

2) literature research on nano-FPGA
A few papers are categorized into 
i) Fault_Toelarant_FPGAs
ii) Nano_Technique
iii) Nano_Modeling
iv) Nano_Programmable_Logic
and are deposited into corresponding directories