In this week, I was working on the following:
1) the simulation of entire design.
Currently, each individual module can work respectively, 
but it needs several additional work when connect them together, 
especially, the size of transistor at the connection needs to be tuned.
For example, as the driver needs to drive a wire with length ~1000um, 
the size of a driver chain needs to be found. 
I've verified the part that connects the test generation with decoder, 
ring oscillator. I'm connecting the lase module, a 8:1 MUX and verifying its functionary. 
It can be done in this week.
2) I've began some simple layout designs based on the library like the inv, nand2 ...;
3) I'm reading several recent papers from Berkeley and Intel/IBM, 
about 60GHz design of RF/MMIC on-chip. As the transmission line (T-line) loss becomes
large in this region, especially the impedance matching 
becomes a trouble for connecting RF/MMIC modules like LNA, VCO with T-lines at different stages.
Automatically design/synthesis of T-line becomes a need to replace the manually based design. 
I'm thinking to extend Sheldon's reduction method and our reduction method in this field. 
One problem I'm thinking is how to generate the s-parameter based sensitivity analysis by reduction.
It will be also related to the topics of the current part-time job.