In this week, I'm working on the follows:
1) I have tested the entire testing circuit together, that includes:
test generate module, interconnect under testing, and ring oscillator;
2) I have found that, 
i) when using 7-stage minimum sized ring oscillator, 
the operating frequency is around 8~9GHz;
ii) when using ring oscillator including a 1000um wire with minimum width
(IBM single wire model), 
the operating frequency s only 2 GHz. 
It is due to the large delay introduced from wire.
As for such a long wire, the size of the 
driving buffer needs to large enough.
I'm enlarge the width to reduce the resistance such that 
hoping to observe a increased opening frequency;
Moreover, I'm wondering if it will be more self-consistent to 
use slew-rate (rising time) as it is more related to inductance; 
3) I'm still working on the layout for each logic circuit;
4) I'm reading papers about possible opt method applied for the impedance matching.