In the past one week I rewrote the ISLPED submission, 
made changes according to the review comments of DAC and ISLPED,
and submitted the paper to ICCD.

Meanwhile I search the literature for current studies
on voltage scaling. I find out that although there has
been extensive studies on voltage scaling with discrete
vdd levels, all of them (as far as I have read) focus
on the scheduling algorithm assuming (1) the number of
discrete vdd levels are fixed; and (2) the value for
each vdd level are given. What we are going to study
differs from them in the sense that our goal is to 
fix the number of Vdd levels and the value of each level. 

Our problem can be: given the characteristics
of a task set (distribution of execution time), decide
the design of voltage scaling circuit with N discrete vdd
levels, such that total power can be minimized under given 
QoS.

There are some starting points we can take. Without considering 
leakage power, first, it has been proved that for each task 
with its execution time, there is one optimal Vdd for minimum power 
while meeting the deadline. Second, with discrete voltage
levels, at most two vdd levels are enough for one task with
a deadline to achieve minimum power. With leakage power
these conclusion may change, which we can try.

I feel these two conclusions may be helpful in our problem
solving and I am still try to make the problem more clear.