The following is the summary of my work in the week of Aug 29 - Sep 4. 

1. Finished the revision of the micro-architecture and floorplanning 
   co-optimization paper. The changes are summarized as follows:

   Experiments: 
	1. Add Fig 1. to show the trajectory of SA and distributions of bus latencies. 
	2. Add Fig 4. to show the accuracy of the TPWL model against the total number of simulations. 
	3. Change 70nm technology to 5GHz in 100nm technology. 

   Writing: 
	1. Title: changed to Microarchitecture configurations and floorplanning co-optimization.
	2. Abstract: Added the data for comparing between the TPWL model and access ratio model. 
	3. Introduction: The first 3 paragraphs are heavily revised. Sachin's paper has been reviewed.
	4. Background: Generation of 70nm has been removed. 
	5. section 3 (TPWL model): major changes in justifying that TPWL can be applied to SA
	6. section 6 (experimt): Orignial figure to show the accuracy of the TPWL model has been 
	   replaced by figure 4.  Table V has been updated. Discussion between TPWL model and access 
	   ratio model has been rewritten. Discussion on the weird data point in issue 4 has been addressed. 
	7. section 7 (conclusion): slightly change on experiment results. 

2. Writting on description of the DC/DC stacked system,  not finished yet.