Weekly Report
Yan Lin 1/29
Work 1: Power-aware routing for mixed FPGA interconnects
 I have finished Approach II using power-aware routing and got some
 results.

 The ratio of Vdd-gateable to Vdd-programmable interconnects is set to be
 1 to 1. Only high-Vdd is applied to Vdd-gateable interconnects. As a
 remainder, Approach I uses single-Vdd routing followed by bottom-up
 assignment.

 The average percentage of low-Vdd switches achieved by Approach I and
 Approach II are 46.22% and 49.85%, respectively. For Vdd-programmable
 interconnects, the segment based bottom-up assignment can achieve
 85.83%.

 The average interconnect power saving achieved by Approach I and
 Approach II are 69.95% and 72.02%, respectively. As reference, the
 interconnect power saving achieved by Vdd-gateable interconnects and
 Vdd-programmable interconnects are 63.68% and 76.32%, respectively. The
 baseline is single-Vdd architecture.

 Both Approach I and Approach II reduce more power compared to
 Vdd-gateable interconnects and consume more power compared to
 Vdd-programmable interconnects. Apparently Approach II can achieve more
 low-Vdd switches and more power saving compared to Approach I. However,
 there is 5.8% performance lost for Approach II due to power-aware
 routing as expected.



Work 2: Analysis of region-based Vdd-gateable/Vdd-programmable interconnects
 Assuming FPGA architecture (N, k) = (10, 4) using Vdd-programmable
 interconnects, I did a quick estimation for area overhead.

 For SRAM area overhead due to Vdd-programmability, the ratio of
 connection switch to routing switch is 0.4:1. For power transistor
 overhead, the ratio of connection to routing switch is 2.06:1.
 Considering both SRAM and power transistor, the ratio of connection to
 routing switch is 1.68:1.

 Considering the ratio, I think it's worthwhile to study region-based
 Vdd-programmable/Vdd-gateable connection block and routing switches.

Work 3: Review TCAD submission paper 
"Realizing Low Power FPGAs:
A Design Partitioning Algorithm for Voltage Scaling and A Comparative
Evaluation of Voltage Scaling Techniques for FGPAs" by
Rajarshi Mukherjee and Seda Ogrenci Memik.

Ongoing work includes analysis of preferred directional routing architecture,
constructing routing resources graph and routing algorithm considering
preferred directional routing architecture.