My work in the past half week includes the following:

1. Journal revision for TCAD paper.
Some of the initial changes have been made.
The part for single Vdd scaling have been removed. 
(I am also thinking that we should remove the dual-Vt FPGA design and use it directly 
as the baseline).
The interconnect power reduction has been included into the journal paper. 


2. Reading papers for FPGA proposals and help the proposal writing.
"Improving FPGA Performance and Area Using an Adaptive Logic Modules", Mike Hutton ect.
"Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size", Vaughn Betz etc.

I will continue to work on the TCAD journal revision. Make a single design flow for both
pre-defined dual-Vdd and programmable Vdd. This will change the organization of the paper.
Also, I will continue to look into charge-recycling design for dual-Vdd FPGAs.