Weekly report Yan 2/20/05

Work 1 TVLSI Journal Revision

VPR and PSim have been performed for FPGA Class 3 using 
Vdd-programmable interconnects w/o level converters.
All the data including energy, delay and area has been
collected and processed for FPGA Class1, Class2 and Class3.
Energy-delay tradeoff figure, energy-area tradeoff figure,
energy breakdown bar figure, area breakdown bar figure
and area overhead breakdown figure have been generated.

Work 2 Preparation for FPGA'05

Slides have been finished and polished for FPGA'05. 

Ongoing work inlcudes pratising presentation for FPGA'05,
programming for local interconnect connectivity statistics
and writing for journal revision.