My work in the past week includes the following:

1. Journal revision for TCAD paper.
Considering that our Psim has adopted a new power model, I am running experiments to update the
data in the journal papers. Basically, the power vs. performance tradeoff curve needs to be updated.
I am choosing the VddH/VddL combinations in the origianl tradeoff curve and update the data, which
includes re-generating the BC-netlist files and run Psim for 5 architectures: arch-SV, arch-hl, arch-PV-hlp
arch-PV(100% P-blocks) and arch-ideal.

So far, the BC-netlist generations have almost been finished. I will continue running the Psim.

Also, I am think that if we can remove the mixed H/L/P and directly go to 100% P-blocks for Vdd-prorammable
FPGAs.

2. Running SPICE experiments for skewed singal and studied how different 
switching patterns affect the interconnect power and delay.

3. Reading related FPGA papers.
"Skew-Programmable Clock Design for FPGA and Skew-aware Placement", M.M.S.