Weekly Report  2/27/05
Yan Lin

I attended FPGA'05 from Feb 20-22. I talked to Mike Hutton and 
Vaughn Betz during conference on Altera Stratix/Stratix II routing
architecture issue. The routing switch design, output connection
block merging technique and buffer efficient input connection block
are clear. The routing switch block deign with uni-directional
switch remains unclear due to confidential reason. I also attended
majority of the presentations. Overall, the experience during this
conference was positive.

For TVLSI journal revision, I've added a subsection discussing
the need for Vdd-programmability. I've addressed the concern about
power transistor sizing for CLBs and using normal-Vt with gate-boosting
rather than high-Vt. I've addressed the reason we can reduce both
delay and dynamic energy by using decoder-based connection block
compared to conventional one.

For TCAD journal co-worked with Fei, I've assisted Fei running Vpr
and Psim for these cases, Vdd-programmable CLBs + VddH interconnects,
Mixed VddH/VddL/VddP CLBs + VddH interconnects, Vdd-programmable CLBs
+ Vdd-P interconnects w/ LCs. 

I've read paper "The Stratix II Logic and Routing Architecture" from Altera and
will give a presentation on Tuesday. There is not much new thing as one of the
the main contributions of this paper, ALM which has been presented in Mike's FPL'03 paper.
Simply claiming performance improvement and area reduction without detailed
discussion makes this paper less insteresting.

The ongoing work includes disscussing area overhead/energy breakdown,
rewriting introduction/conclusion and addressing
other minor issues in review comments for TVSLI revision, 
collecting experimental results for Fei's TCAD revision.