In this week, I have worked on the following aspects:

(1) I have spent most of time in the writing for the micro proposal.
The novelty of the proposed block-structural-model-reduction (BSMOR) is 
finalized as two aspects: (i) BSMOR can generate more compact model; 
(ii) a hierarchical partition after reduction can alleviate the 
computation complexity introduced by ports.
 
(2) I debugged the implementation of BSMOR and PRIMA both with 
sparse matrix data structure. 
(i) To show the effectiveness of model reduction, i.e., 
under the same accuracy (error difference to the original model) 
comparing the reduction converging time, 
I have found for a 80K (with 10 ports) circuit, 
the run time of BSMOR(block 16x16) is (288s),
SPRIM is (562s), and PRIMA is (960s); 
(ii) To show the ability to handle large number of ports by using partition, 
I have found that for a 300K circuit (250 port), 
the partitioned model is about 40X faster 
than the flat one (280s vs 6s). 

(3) I'm working on more larger examples by just increasing the port number.
I expect to check following aspects when increasing port number:
(i) if BSMOR will be more efficient during model reduction compared to PRIMA; 
and (ii) when the flat macro-model will become intractable/inefficient.