In the past week I focus on Journal revision for the 
power gating paper. The main changes include:

1. Revise the introduction to discuss related work
on cache decay method pointed out by the reviewers,
and clearly state our contributions which include
(1) study the microarchitecture level leakage power
characteristics for the whole processor, but not
merely cache hierarchy or function units; (2)
propose a systematic approach to evaluate the
efficiency of microarchitecture level leakage 
power reduction techniques and pinpoint the
appropriate candidate components under given 
techniques; (3) show the leakage power reduction
techniques on specific component such as caches does
not necessarily reduce the leakage energy of the whole 
processor, as such technique may lead to excessive 
running time and excessive leakage energy from other 
component; and (4) study the realistic leakage power 
reduction on cache with data retention and show the 
leakage reduction techniques with data retention is 
better than cache decay without data retention

2. Implement cache decay method with fix interval and 
adaptive interval adjusted by feed-back control mechanism.

3. Write the revision summary.

I also make change in our DAC submission by incorporating
the new performance model, and also change some writing.