In the past one week I worked on journal revision of power gating paper
and the revision of our DAC submission. The journal revision has been
finished. I modified the section of leakage energy characteristic and 
ideal power gating with updated results, and rewrote the section of
realistic power gating. In this section of the new draft, we apply VRC 
with data retention ability to cache decay method, and compare the results to
the original cache decay method without data retention. We show that cache
decay with data retention on L2 cache can reduce performance penalty by 7% and
increase energy saving by 12%. Furthermore, we show that the excessive whole chip leakage
energy introduced by additional execution time due to performance penalty
may exceed the leakage energy saving on individual components,
and conclude that studies on leakage energy reduction
should evaluate its effectiveness from the whole chip point of view, instead
of focusing on individual components.

The submission revision is on progress. The abstract and introduction have
been finished. The contribution is explicitily stated as
(1) To facilitate our study and avoid the tremendous
simulation overhead when exploring the multi-dimensional
design space for voltage scaling in CMP, we develop an
analytical performance model to estimate the on-chip communication overhead
in a CMP system. Our performance model is able to consider
different $V_{dd}$ for different processing cores, and
achieves less than 15% error compared to cycle accurate simulation.
(2) We show the single power domain is sufficient for voltage
scaling to reduce dynamic power. However, with
the ever increasing leakage power in the deep sub-micron
design era, multiple power domains are necessary
for efficient voltage scaling in CMP.
(3) We study the problem of power minimization consider
on-chip power supply constraints with multiple power domains.
We show that given power supply cost models, a cost-optimal on-chip
power supply solution without considering leakage leads to 28.6% 
higher power than a leakage-aware cost-optimal solution. Therefore, 
optimal power supply solutions for voltage scaling in CMP are
only achieved when considering both dynamic and leakage power.

The performance model has already been updated. I am working on
the sections of problem formulation and experimental results.