In the past one week I mainly worked for ISLPED submission.

Besides, there are a few papers I read:

1. Y. Li et al, "Understanding the energy efficiency of SMT",
ISLPED 04.

This paper studies the energy efficiency of SMT for a POWER-4
like microarchitecture with a PowerPC simulator. First they
define the baseline processor, and then they study SMT by
increasing the size of a number of key structures by a
certain factor, such as instruction buffer, rob, reservation 
stations and physical registers, compared to the baseline processor. 
After that they run the simulator and obtain the results.
The conclusion is that SMT can provide a performance speedup
of nearly 20% with a power overhead of roughly 24%. Therefore
SMT is energy-efficient in terms of energy-delay^2.

The authors are those people who developed hotsopt.

2. Y. Li et al, "Performance, energy and thermal considerations
for SMT and CMP architectures", HPCA 05

The conference was in last week. This paper study both SMT and CMP.
The same area requirement is set for SMT and CMP, and Shared L2 cache
is assumed for both of them. Since CMP duplicate cores while SMT
only duplicate a number of key structures, CMP dedicates more area
for pipeline cores and has smaller L2 cache. For this reason, SMT
becomes superior for memory-bound benchmarks. CMP, however, performs
better for cpu-cound benchmarks. For thermal consideration, SMT
heating is primarily caused by localized heating in certain key 
structures, while CMP heating is caused by the global impact of
increased energy output.