In the past one week I worked on Mindspeed review slides, study
dynamic power management on multi-processor systems with
voltage and freqency scaling, and read a few related papers.

There are some studies on the traditional dynamic power
management on multiprocessor systems, focusing on task
scheduling. There is dependency between tasks more or less.
Our case is somewhat different as there is no dependency
between tasks (packets to process). Besides, our focus
should be CMP considering on-chip power supply modules.
There are a few things on the todo list:
1. constructure the abstract model for VRMs to use at 
microarchitecture level.
2. setup the model for dynamic workload characteristics.
The total incoming packet rate has a normal distribution
with parameters to be referred from VoIP papers in the 
literature.
3. implement the shared cache in our CMP simulator. 

Some interesting papers include:
1. L. Hammond et al, "A single-chip multiprocessor", IEEE 
Micro 1997.

Envisioning the era of billion-transistor-on-a-chip, 
this paper discusses three possible architecture to
make use of all the massive amount of transistors. They
are: (1) wide issue-width superscalar; (2) SMT; and (3)
CMP. The conclusion is superscalar can not be efficient
due to its complexity. SMT can provide substantial
performance increase but fall short of CMP due to 
wire delay and bandwidth requirement. This is an interesting 
point and can be further explored. Last year in MICRO
there was a paper claiming the wire delay is not a 
problem for SMT and provide the pipelined memory
to meet the SMT bandwidth requirement. However none of
these studies considers realistic floorplan of SMT. Therefore
all these conclusions are not so persuasive when it
comes to the wire delay.

2. D. T. Marr et al, "Hyper-threading technology architecture
and microarchitecture", Intel Technology Journal, 2002

This paper discusses the implementation of hyper-threading
technology in Xeon.