wing is the summary of my work in this week: 

	1. Analyze the power consumption of the PWM circuit and try to
           find out the reason for the low power efficiency. It turns out
           that main power loss occurs on the conduction loss of power
           transistors. To reduce that power loss, we can try to enlarge
           the size of the transistor and so reduce the Ron (on resistance).
           But increase the size of transistor will also cause the parasitic
           capacitance to increase and so the switching power will also
           increase. There will be an optimized point and I am runing
           simulations to confirm it.

        2. Updates the powerpoint file for PWM project. I will keep updating
           it once I have some new results with higher power efficiency.

        3. Run the hspice simulation to generate the rlgc matrices for
           the s-parameter extraction. Hspice supports W element to model lossy
           transmission line. Moreover, Hspice also has a built-in 2D field
           solver to compute the rlgc for the interconnects. I get the rlgc
           matrices and sent it to yiyu. Also, try debugging the TRIO2 program.


	- Wei