The following is the summary of my work in the week of Sep 12 - Sep 18. 

1. Tune the PFM parameters under a 2-level stacked system. conclusions:   
	a). If the inductance of the LC filter is too small, to maintain   
            a low voltage ripple, the openning time of the power P transistor
            has to be small. The power efficiency of the PFM is brought down 
            by the delay of the current comparator. So, the inductance has 
            to be big and can't be integrated in the chip under 
            current design.
	b). The current of the bottom loading must be smaller than the 
            top loading. Otherwise, the voltage level of top loading can't 
            be maintained because PWM keeps charging the capacitance of  
            the capacitor of the PFM. I have tried to use a bypass transistor
            which is parallelly connected with the top loading and closed
            when the voltage level is higher than reference level. However, 
            it brings down the total efficiency. 
2. Develop scripts to scan the loading and runs simulations for a couple 
   of times.  
3. Integrates Sasank's PWM setting into the 2-level stacked system.