During this week, I have worked on the follows:

1) finished experiments for 3D via allocation:
1.1) comparing temperature profiles after via allocation 
considering transient part and not considering the transient part.
1.2) runtime scalability experiments, comparing with full model.
1.3) finished the draft in first run.

2) prepared the journal submission of TBS;
2.1) changed introduction part to a structured P/G design for 3D ICs. 

3) preparing the testing measurement of chip.