During this week, I have worked on the follows:

0) working on ISLPED submission; read power and clock gating 
from Intel, Majid, and Luca Benni. rewrite and redo the parts 
for transient thermal-power input;

1) verify/test the code of TBS, BVOR and SP-MACRO.
exchange data and test with ADI;

2) work on PCB design with Yiyu;

3) begin coding for multi-level structured and parameterized reduction; 
Sachin's paper only considers pitch, and Charlie's paper only considers width.
Sachin has congestion cost for adding P/G wires or changing the pitch.
The current density constriant is not realted wire width.