During these two weeks, I have worked on the follows:

0) work with yiyu to prepare the measurement of chip;

1) finished journal version for bvor and 
working on journal version for tbs;

3) discuss with yu about clock synthesis:
figured out a parameterization approach for clock tree optmization;
3.1)due to logic power correlation, 
the temperature distribution has correlation;
3.2) by taking the time-domain snapshots of temperature, 
we can construct a correlation matrix which is low rank;
3.3) using SVD we can find the rank number (k) of the correlation matrix;
as such, we can do a k-means clustering to find k clusters and their centers.
3.4) hence the orignal parameterized system can be partioned into 
k clusters, where all parameters in one cluster can be treated similarly.
This can be extended into parameterized reduction considering process
variation.  

4) read papers on driver modeling in timing analysis;