During this week, I have worked on the follows:

0) worked on the book and replaced bvor by tbs method;

1) finished the code of new VNA reduction, 
i.e., the L^-1 reduction;

2) finished code of power/ground via stapling to minize volatge drop;
2.1) use TLOS approach. the design freedom is 
via stapling pattern and via density for each pattern;
the objective is to minize via number;
the constraint is maxium volatge drop;
2.2) use structured and paramterized reduction with VNA;
2.3) generating large examples; 

3) working on adding thermal constraint; 
the same prcocedure can be used for thermal-PG wire design for joanna.