During this week, I have worked on the follows:

1) work on dac final version;

2) discuss with Yu about clock synthesis:
3.1) based on Sachin's previours paper, 
I think we can intrdouce a second desgin freedom wire-size 
such that we can use it to calculate second-order moment 
to analytically generate an accurate dealy model for clock-tree;
3.2) with the use of the calculated sizing result from the accurate 
delay model, we can modify the parameterization method 
to efficiently update the temperature profile repeatedly.

3) work on bvor journal submission. I'll combine bsmor and bvor paper.
I think it can be done in this week.