During this week, I have worked on the follows:

0) work with yiyu to prepare the measurement of chip;

1) work on bvor journal version;

2) discuss with joanna about how to embed 
thermal/power sensitivity into multi-level routing;

3) discuss with yu about clock synthesis:
figured out a parameterization approach for clock tree optmization;

4) read papers on (i) model reduction considering correlated variation 
by orthogonal polynomial expansion; (ii) nonlinear cirucit behavior
extraction.