A Brief Survey for Retiming Literature

by Yu Hu, Nov. 27, 2005

A. Basic Conceptions in Retiming:

1) Retiming synchronous circuitry

2) Continuous Retiming: Algorithms and Applications

B. Placement and clustering with retiming:

1) Clock period minimization:

i. Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization

ii. Optimal Clock Period Clustering for Sequential Circuits with Retiming

iii. Physical Planning with Retiming

iv. Multilevel Global Placement with Retiming

2) Min-area by simultaneously budgeting and retiming

i. Delay budgeting in sequential circuit with application on FPGA placement

ii. Minimum-area sequential budgeting for FPGA

C. Post-stage retiming

1) Integrating Logic Retiming and Register Placement

D. Retiming and pipelining for FPGA technology mapping (by Jason Cong):

1) FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits

2) Optimal FPGA Mapping and Retiming with Effiecient Initial State Computation

3) An Improve Algorithm for Performance Optimal Technology Mapping with Retiming in LUT-Based FPGA Design

4) An Efficient Algorithm for Performance-Optimal FPGA Technology Mapping with Retiming

E. Glitch Power Minimization by Pipelining and Retiming

1) Reducing the Power Consumption of FPGAs through Retiming

2) Retiming Sequential Circuits for Low Power

3) The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

4) Retiming-Based Logic Synthesis for Low-Power

5) Low Power Logic Synthesis under a General Delay Model

F. Power Minimization by delay budgeting and retiming:

1) Unification of Basic Retiming and Supply Voltage Scaling to Minimize Dynamic Power Consumption for Synchronous Digital Designs

G. Others:

1) SIS: A System for Sequential Circuit Synthesis

2) Simultaneous Timing Driven Clustering and Placement for FPGAs