Yu's work from Oct. 31 to Nov. 6

1. finish the homework2 of M209, which is to implement a module order reduction algorithm by matlab.
2. finish the homework2 of M202, which is to implement a system in an embedded system, including the coding and reports.
3. begin to implement the retiming for sequential FPGA vdd assignment. Todo list of the implementation is as follows.
	3.1 re-construct the timing graph in VPR. The original timing graph in VPR treats FFs as primal input/output nodes, 
		to retime the circuit, I need to re-construct the timing graph so that the new timing graph is from PI to PO 
		and all FFs are treated as edge weights in the graph.
	3.2 formulate the retiming&budgeting problem to the LP problem and solve it
	3.3 based on the retiming and budgeting results, reassign the FFs and slacks and re-construct the timing graph in VPR,
		then, use the bottom-up reassignment and refinement to assign vdd to buffers in the routing trees
	3.4 if the results are ok, I'll implement the min-cost flow formulate and solve it
		otherwise, I'll check the problem in the problem formulation
   currently, I just began to work on 3.1 as I was quite occupied by the courese projects. It's expected to get some initial
	results before the end of the next week.