Yu's work from Nov. 7 to Nov. 13, 2005

1. Finish coding on LP formulation and FF assignment for simultanous retiming and budgeting problem. 
   I tested a sequential circuit "tseng", and found that the total power reduction after retiming 
   reduced 10% than the alg. without retiming (currently I can just get the evaluation value of power
   instead of PSim simulation because vdd assignment hasn't done). But, when I assigned FFs based on
   the formulatio solution, I found that some FFs are assigned to edges where FFs can't be inserted.
   The causation of this problem is that VPR does not allow us to access LUT and FF independently.
   It's a way to avoid this problem by modifying placer in VPR, but I am not sure how much effort
   I will pay for this. The other way is to add more timing constraints in. I'm going to test this
   way first.
2. Finish homework #3 for M202, which includes 7 problems.
3. Paid some efforts on the final project for M202.