In this week, Yu has completed the following works.
1. Derived a MILP formulation for power optimal simultaneously budgeting and retiming. The details of my formulation are in [vdd_retime_milp.pdf].
2. Got a license from www.mosek.com in horoscope, which enable us to calculate large MILP problems.
3. I've implemented the above formulation and tested two sequential FPGA designs, tseng and bigkey. For bigkey, we got 10\% power reduction compared to the budgeting result without retiming. The calculation time for MILP is about 60 seconds with mosek (www.mosek.com). The detailed results are shown in [retime_res.doc]
4. Made a brief survey for retiming related works [retime_survey.html]. I've upload all papers involved in the survey in http://eda.ee.ucla.edu/member_only/retiming Due to the time limitation, I haven’t read through all papers list yet, but just listed the categories of each paper. I'll add my comments on when I get some time. The main conclusions are:
a) Little work is done for low-power FPGA in placement with retiming. Most existing works are focused on clock period minimization or area minimization. Retiming in placement is not mainly used in ASIC instead of FPGA.
b) Jason Cong's retiming for FPGA is mainly focused on technology mapping. Their retiming in placement is performed in ASIC.
5.
Finish m
To do list in the next week:
1. Compare simultaneous retiming and budgeting results to sequential retiming and budgeting approach. And test more circuits.
2. Study on statistic gate sizing problem.
3.
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