4B Sequential Circuit Optimization
4B.1 Trade-off between Latch and Flop for Min-Period Sequential Circuit Designs with Crosstalk
4B.2 Flip-Flop Insertion With Shifted-Phase Clocks For FPGA Power Reduction
4B.3 Acyclic Modeling of Combinational Loops
5A Variability in Design
5A.1 DiCER: Distributed and Cost-Effective Redundancy for Variation Tolerance
5A.2 Worst-Case Analysis to Obtain Stable Read/Write DC Margin of High Density 6T-SRAM-Array with Lo
5A.3 Noise Margin Analysis for Dynamic Logic Circuits
6B Technology Mapping and Timing Analysis
6B.1 Statistical Technology Mapping for Parametric Yield
6B.2 Reducing Structural Bias in Technology Mapping
6B.3 Improving the Efficiency of Static Timing Analysis with False Paths
8B Timing and Power Optimization
8B.1 Statistical Critical Path Analysis Considering Correlations
8B.2 Discrete Vt Assignment and Gate Sizing Using a Self-Snapping Continuous Formulation
8B.3 Formalizing Designer's Preferences for Multiattribute Optimization with Application to Leakage-
8C System-Level Variability Modeling
8C.1 Projection-Based Performance Modeling for Inter/Intra-Die Variations
8C.2 System-Level Power and Thermal Modeling by Othogonal Polynomial based Response Surface Approach
8C.3 Accurate Estimation and Modeling of Total Chip Leakage Considering Inter- and Intra-Die Process
9C Statistical Timing Analysis
9C.1 Statistical Timing Analysis With Two-sided Constraints
9C.2 A Unified Framework for Statistical Timing Analysis With Coupling and Multiple Input Switching
9C.3 Defining Statistical Sensitivity for Timing Optimization of Logic Circuits With Large-Scale Pro
11C Statistical Optimization
11C.1 Parametric Yield Maximization using Gate Sizing based on Efficient Statistical Power and Delay
11C.2 Gate Sizing Using Incremental Parameterized Statistical Timing Analysis
11C.3 Statistical Gate Sizing for Timing Yield Optimization