Yu's work on this week

1. completed works
* finish reading source code of vpr placement
* finish implementation of wire retiming algorithm
* read some papers to help my understanding integarting retiming and placement in FPGA
* paper reading and discussion with Prof. Jing, pipeline-aware CAD algorithm and routing-poor architecture for FPGAs are studied
* finish doing M209S and M236B labtories and assignments.

2. works under processing
* integrating retiming algorithm into SA-based placement in vpr