NOTE:
This list is divided based on structure of clock network (tree or mesh), design
freedom (topology changing, routing, buffering and wire sizing) and
optimization objective (tolerance to process variations and thermal issues).
Tree
n
Summery
u
Jeng-Liang Tsai, Clock Tree Synthesis for Timing
Convergence and Timing Yield Improvement in Nanometer Technologies, Ph.D.
dissertation, UNIVERSITY OFWISCONSIN-MADISON, 2005.
u
Jascon Cong, Lei
He, Cheng-Koh Kok and
Patrick Madden, Performance Optimization of VLSI
Interconnect Layout, Integration 97.
n
Non-buffered
u
Deterministic
l
Zero-Skew
1.
Ren-Song Tsay, An Exact Zero-Skew Clock Routing
Algorithm, TCAD93
2.
Masato Edahiro, A Clustering-Based Optimization
Algorithm in Zero-Skew Routings, DAC93
3.
Ting-Hai Chao, et al, Zero Skew Clock Routing with Minimum
Wirelength, TCAD92.
l
Bounded-Skew
1.
JASON
CONG, ANDREW B. KAHNG, CHENG-KOK KOH, and C.-W. ALBERT TSAO, Bounded-Skew Clock and Steiner
Routing, ACM Trans. On DAC, 1998
2.
Rishi Chaturvedi and Jiang Hu, An Efficient
Merging Scheme for Prescribed Skew Clock Routing, TCAD05.
3.
Chung-Wen Albert Tsao and Cheng-Kok Koh, UST/DME: A Clock Tree Router For General Skew Constraints, ICCAD00.
l
Daksh Lhther and Sachin S. Sapatnekar, Moment-based
techniques for RLC clock tree construction, TCASII98.
u
Process Variation
l
Bing Lu, Jiang Hu, Gray
Ellis and Haihua Su, Process Variation Aware Clock Tree
Routing, ISPD'03.
l
Bing Lu, Jiang Hu, Gray
Ellis and Haihua Su, Statistical Clock Tree Routing for
Robustness to Process Variations, ISPD'06.
u
Thermal and
Power
l
Minsik Cho, Suhail Ahmed and David Z.
Pan, TACO: Temperature Aware
Clock-tree Optimization, ISPD'06
l
Gustavo E. Tellez, Amir
Farrahi, and Majid Sarrafzadeh, Activey-Driven
Clock Design. TCAD01.
n
Buffered
u
Deterministic
l
Chung-Ping
Chen, Yao-Wen Chang and D. F. Wong, Fast Performance-Driven
Optimization for Buffered Clock Trees Based On Lagrangian Relaxation,
DAC96.
l
Rishi Chaturvedi and Jiang Hu, Buffered Clock Tree for High
Quality IC Design, ISQED'04.
u
Process Varaitions
l
Chung-Ping
Chen et al, Process-Variation
Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected
Scan-Line Sampling, ASP-DAC'05.
l
Jeng-Liang
Tsai, Lizheng Zhang and Charlie Chung-Ping Chen , Statistical Timing Analysis
Driven Post-Silicon-Tunable Clock-Tree Synthesis, ICCAD'05
n
Wire sizing
u
Jeng-Liang
Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen, Signma-Optimal
Minimum-Delay/Area Zero-Skew Clock Tree WireSizing in PseudoPolynomial Time,
ISPD03.
u
Anand Rajaram , Bing Lu†, Wei Guo‡, Rabi Mahapatra ,
Jiang Hu, Analytical Bound for Unwanted Clock
Skew due to Wire Width
Variation, ICCAD03
n
Buffer insertion and wire sizing
u
Ashish D.
Mehta, Yao-Ping Chen, Noel Menezes,
D.F. Wong, and Lawrence T. Pileggi, Clustering and Load Balancing for Buffered Clock
Tree Synthesis, ICCD97.
u
Jeng-Liang
Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen, Zero
Skew Clock-Tree Optimization With Buffer
Insertion/Sizing and Wire Sizing, TCAD04.
n
BST Source Code by A.B. Kwang
Non-Tree (Mesh
or hybrid)
n
Buffered
u
Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil Khatri, Practical Techniques to
Reduce Skew and Its Variations in Buffered Clock Networks, ICCAD05
u
Anand Rajaram， David Pan, Variation Tolerant Buffered Clock Network
Synthesis with Cross Links, ISPD06
n
Non-buffered
u Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong and Sheldon Tan, A Fast Delay Computation For the Hybrid Structured Clock Network, IEICE Trans. On Fundamentals, 2005.
u
Anand Rajaram， David Pan, Jiang Hu, Improved Algorithms for
Link-Based Non-Tree Clock Networks
for Skew Variability Reduction, ISPD05.
u
Anand Rajaram， David Pan, Fast
Incremental Link Insertion in Clock Networks for Skew Variablity Reduction,
ISQED00.
u
Anand Rajaram, Jiang Hu and Rabi Mahapatra, Reducing Clock Skew Variability
via Cross Links, DAC04
u
Haihua Su and Sachin
S. Sapatnekar, Hybrid Structured Clock Network
Construction, ICCAD01