In the last week, Yu has done the following work.

1. prepare materials for TOP exam, passed on Friday
2. working with Prof. Jing for my TCAD special issue for the ISPD'06 paper (Steiner tree)
3. prepare for the DAC final version, I'll release the one that I revised based on comments and double check with Yan on Monday
4. continue working on the FPGA retiming coding to implement placement -> retiming -> routing -> retiming to see the interactive 
   of retiming between different CAD flow. The coding has been completed. I need two to three more days to debug and test.
5. paper reading: 
   1. Cristinel Ababei, Hushrav Mogal, and Kia Bazargan, "Three-dimensional Place and Route for FPGAs", TCAD
   2. Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, and Sachin Sapatnekar, 
      "Placement and Routing in 3D Integrated Circuits", IEEE Design & Test of Computers.
   comments: both of these two works are presented by people from University of Minnesota. 
             They developed a package, namely TPR, similar to VPR, for 3D FPGA placement and routing. 
             The extension of architecture from 2D to 3D FPGAs is natural: change the switch box from square to cube,
             the vertical connection in a 3D switch box plays the same function as the stack via. Compared to 3D ASICs,
             [2] pointed out that 3D FPGAS have less power density so that the thermal issue is not the main problem,
             and the main challenge in 3D FPGAs is overhead of pass transistors and buffers to implement the 3D interconnect,
             specically, the inter-die vias are valuable resource. Therefore, FPGA architecture and chip co-design is a
             good potential research direction. An algorithm to assign routing resource (including switch box and routing channel)
             reasonable and keep the routability in the same can potentially reduce the chip area and performance.
    All these papers have been updated to http://eda.ee.ucla.edu/member_only/Routing_ProcessVariation/3D%20FPGA/.