Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology

Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali and Steve H.-C. Yen

This paper addresses post-routing capacitance extraction during performance-driven layout. We first show how basic drivers in process technology (planarization and minimum metal density requirements) actually simplify the extraction problem; we do this by proposing and validating five ``foundations'' through detailed experiments with a 3-D field solver on representative 0.50um, 0.35um and 0.18um process parameters. We then present a simple yet accurate 2 1/2-D extraction methodology directly based on the foundations. This methodology has been productized and is being shipped with the Cadence Silicon Ensemble 5.0 product. We conclude that the 2 1/2-D approach has sufficient accuracy for current and near-term process generations. An extended abstract of this paper can be found in the proceedings of ACM/IEEE Design Automation Conference, Anaheim, CA, June 9-13, 1997.