This paper presents a switch level fast timing simulator, FTSIM, to
verify the logic behaviour and timing performance for MOS digital circuits
for both prelayout and post-layout. The circuits are first partitioned
into DCCs (DC-connected component), then the charging and discharging of
each output node of a DCC is modeled by a macromodel, retaining the
nonlinearity of the transistors, and its characteristic equation is
computed using a voltage incremental technique. In addition, a heuristic
event-driven self-adaptive window algorithm is proposed to speed up
waveform convergence when feedback is present at DCC level. Test results
with benchmark circuits from industry show a speed up of 2 to 3 orders of  
magnitude over SPICE for medium scale circuits with typical 5% timing
accuracy loss, and the speed up is nearly linear with the circuit size.