In the last week, I was working on the following.

- submitted TCAD revision II (pdf)

- come up with the detailed todo list for time slack allocation with process variation project (pdf)

- writing derivation in progress (pdf)

- finished SPICE simulation for 7x buffer considering process variations. Vth and Leff are considered for delay. Vth, Leff and Tox are considered for leakage. 10~15 data points are sampled within -3sigma to 3sigma range. Three cases, VddH, VddL and Power-gating are considered for delay and leakage. Curve fitting is performed to get the parameters.

- Ongoing work includes derivation, SPICE simulation for 15X buffer and TCAD review. Also read majid's time slack budgeting iccad04 paper.