In the last week, I was working on the followings,
- paper reading
* "Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages", D. Chen et al, FPGA"04
* "Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages", D. Chen and J. Cong, ISLPED'04
The ideas of the above two papers are similar. The formulations are to perform technology mapping/clustering and Vdd-level assignment for LUT/cluster simultaneously under depth constraints. Both first enumerate cuts/clusters, then select cut/cluster considering depth constraint and power with dual-vdd. However, the assignment will be invalid after placement and routing due to interconnect delay. Therefore, I believe post-layout stage is the right stage for Vdd-level assignment.
- summary and proposed ideas for technology mapping (link)
- observation, motivation, proposed problem formulation and algorithms for timing-yield driven Vdd-level assignment with process variation. (link)