| addNode(RtlNode *node) | oagFpga::RtlGraph | |
| bbNodes | oagFpga::RtlGraph | [protected] |
| binaryBusInputOutputOpt(RtlNode::OptType ot, int numOutBits, vector< BBRef > &in1, vector< BBRef > &in2, vector< BBRef > &out) | oagFpga::RtlGraph | |
| binaryBusOpt(RtlNode::OptType ot, vector< BBRef > &in1, vector< BBRef > &in2) | oagFpga::RtlGraph | |
| binaryOpt(RtlNode::OptType ot, BBRef in1, BBRef in2) | oagFpga::RtlGraph | |
| bitMux(BBRef in1, BBRef in2, BBRef sel) | oagFpga::RtlGraph | |
| bitSeq(RtlNode::SeqType st, BBRef D) | oagFpga::RtlGraph | |
| bitSeq(RtlNode::SeqType st, BBRef D, BBRef clock, BBRef aLoad, BBRef aData) | oagFpga::RtlGraph | |
| buildNetlist() | oagFpga::RtlGraph | [inline] |
| busMux(vector< BBRef > &in, vector< BBRef > &sel) | oagFpga::RtlGraph | |
| busMux(vector< BBRef > &in1, vector< BBRef > &in2, vector< BBRef > &sel, vector< BBRef > &outputs) | oagFpga::RtlGraph | |
| CONSTANT0_BBREF | oagFpga::RtlGraph | [protected] |
| CONSTANT1_BBREF | oagFpga::RtlGraph | [protected] |
| constantOne() const | oagFpga::RtlGraph | [inline] |
| constantZero() const | oagFpga::RtlGraph | [inline] |
| currentTraversalID | oagFpga::RtlGraph | [protected] |
| dataBBNodes | oagFpga::RtlGraph | [protected] |
| getBBNodeNum() | oagFpga::RtlGraph | [inline] |
| getExternalTerminalConnection(BBRef terminal) const | oagFpga::RtlGraph | [inline] |
| getFanin(BBRef x) | oagFpga::RtlGraph | [inline] |
| getFanout(BBRef x) | oagFpga::RtlGraph | [inline] |
| getNextState(BBRef seq) const | oagFpga::RtlGraph | [inline] |
| getNode(BBRef ref) const | oagFpga::RtlGraph | [inline] |
| getNodeOptType(BBRef ref) const | oagFpga::RtlGraph | [inline] |
| getNodeSeqType(BBRef ref) const | oagFpga::RtlGraph | [inline] |
| getNodeType(BBRef ref) const | oagFpga::RtlGraph | [inline] |
| getNull() | oagFpga::RtlGraph | [inline, static] |
| getNumOutputBits(BBRef x) const | oagFpga::RtlGraph | [inline] |
| getOutputBit(BBRef ref) | oagFpga::RtlGraph | [inline] |
| getPrimaryBBID(BBRef x) const | oagFpga::RtlGraph | [inline] |
| getTerminalDriver(BBRef terminal) | oagFpga::RtlGraph | [inline] |
| getTransitiveFanin(BBRef x, list< BBRef > &transitiveFanin, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanin(BBRef x, vector< BBRef > &transitiveFanin, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanin(list< BBRef > x, list< BBRef > &transitiveFanin, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanin(list< BBRef > x, vector< BBRef > &transitiveFanin, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanin_recursive(BBRef x, vector< BBRef > &transitiveFanin, bool includeRoots, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanin_recursive(BBRef x, list< BBRef > &transitiveFanin, bool includeRoots, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanout(BBRef x, list< BBRef > &transitiveFanout, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanout(BBRef x, vector< BBRef > &transitiveFanout, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanout(list< BBRef > x, list< BBRef > &transitiveFanout, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanout(list< BBRef > x, vector< BBRef > &transitiveFanout, bool includeRoots=true, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanout_recursive(BBRef x, vector< BBRef > &transitiveFanout, bool includeRoots, bool crossSequential=false) | oagFpga::RtlGraph | |
| getTransitiveFanout_recursive(BBRef x, list< BBRef > &transitiveFanout, bool includeRoots, bool crossSequential=false) | oagFpga::RtlGraph | |
| hasCombinationalCycle() | oagFpga::RtlGraph | |
| hasCombinationalCycle_recursive(BBRef x, unsigned int startingTraversalID) | oagFpga::RtlGraph | |
| hasFanout(BBRef x) const | oagFpga::RtlGraph | [inline] |
| isFunctional(BBRef x) const | oagFpga::RtlGraph | [inline] |
| isNull(BBRef ref) | oagFpga::RtlGraph | [inline, static] |
| isSequential(BBRef x) const | oagFpga::RtlGraph | [inline] |
| isTerminal(BBRef x) const | oagFpga::RtlGraph | [inline] |
| isVisited(BBRef x) const | oagFpga::RtlGraph | [inline] |
| Manager class | oagFpga::RtlGraph | [friend] |
| markVisited(BBRef x) | oagFpga::RtlGraph | [inline] |
| ModuleCompiler class | oagFpga::RtlGraph | [friend] |
| newNode() | oagFpga::RtlGraph | |
| newTerminal(BBRef driver) | oagFpga::RtlGraph | |
| newTraversalID() | oagFpga::RtlGraph | |
| NULL_BBREF | oagFpga::RtlGraph | [protected, static] |
| print(ostream &os) | oagFpga::RtlGraph | |
| print(ostream &os, RtlNode *node) | oagFpga::RtlGraph | |
| removeFromFanout(BBRef x, BBRef fanout) | oagFpga::RtlGraph | |
| RtlGraph() | oagFpga::RtlGraph | [inline] |
| setExternalTerminalConnection(BBRef ref, void *connection) | oagFpga::RtlGraph | [inline] |
| setTerminalDriver(BBRef terminal, BBRef driver) | oagFpga::RtlGraph | |
| unaryBusInputOutputOpt(RtlNode::OptType ot, int numOutBits, vector< BBRef > &in1, vector< BBRef > &out) | oagFpga::RtlGraph | |
| unaryBusOpt(RtlNode::OptType ot, vector< BBRef > &ins) | oagFpga::RtlGraph | |
| unaryOpt(RtlNode::OptType ot, BBRef driver) | oagFpga::RtlGraph | |
| unmarkVisited(BBRef x) | oagFpga::RtlGraph | [inline] |
| ~RtlGraph() | oagFpga::RtlGraph | [inline] |
