Here is a list of all class members with links to the classes they belong to:

- a -

• action : oagFpga::VerilogDesign::Case, oagFpga::VerilogDesign::AlwaysBlock, oagFpga::VerilogDesign::Function
• aData : oagFpga::VerilogSynthesis::ProceduralState, oagFpga::RtlNode::RtlSeqNodeInfo
• ADD : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• addConditional() : oagFpga::VerilogSynthesis::LvalRef
• addGlobalClock() : oagFpga::MapperUtils
• addGlobalReset() : oagFpga::MapperUtils
• addLeafLibrary() : oagFpga::Synthesis
• addLeafView() : oagFpga::Synthesis
• addNode() : oagFpga::RtlGraph
• addTrivialGates() : oagFpga::FpgaMapper
• ai : oagFpga::Manager
• AiModGraph : oagFpga::Manager
• AiModRef() : oagFpga::AiModRef
• aiRef : oagFpga::RtlNode
• aLoad : oagFpga::VerilogSynthesis::ProceduralState, oagFpga::RtlNode::RtlSeqNodeInfo
• AlwaysBlock() : oagFpga::VerilogDesign::AlwaysBlock
• alwaysBlocks : YYSTYPE, oagFpga::VerilogDesign::Module
• AND : oagFpga::VerilogDesign::Instantiation
• andOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler, oagFpga::AiModGraph
• annotateAsynchronousSignal() : oagFpga::ModuleCompiler
• appendSuffix() : oagFpga::VerilogSynthesis
• arguments : oagFpga::VerilogDesign::Primary
• arithmeticAdd() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• arithmeticDivide() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• arithmeticModulo() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• arithmeticMultiply() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• arithmeticSubtract() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• assign : oagFpga::VerilogDesign::Statement
• Assignment() : oagFpga::VerilogDesign::Assignment
• assignment : YYSTYPE
• assignments : YYSTYPE, oagFpga::VerilogDesign::Module
• assignMultiRef() : oagFpga::Synthesis

- b -

• bb : oagFpga::MultiRef
• bbg : oagFpga::Manager
• bbNodes : oagFpga::RtlGraph
• BBRef2AiRef() : oagFpga::ModuleCompiler
• begin_end : oagFpga::VerilogDesign::Statement
• binaryBusInputOutputOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
• binaryBusOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
• binaryOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
• bitMux() : oagFpga::RtlGraph
• bits : YYSTYPE
• BITS_PER_RAND : oagFunc::SimOcc, oagFpga::SimMod
• bitSeq() : oagFpga::RtlGraph
• bitWidth : oagFpga::VerilogDesign::Primary, oagFpga::Synthesis::ConstantValue
• BITWISE_AND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_NAND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_NOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_NOT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_OR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_XNOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• BITWISE_XOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• block : oagFpga::VerilogDesign::Statement
• BLOCK : oagFpga::VerilogDesign::Statement
• BLOCKING_ASSIGNMENT : oagFpga::VerilogDesign::Statement
• blockingAssignments : oagFpga::VerilogSynthesis::ProceduralState
• BOTH : oagFpga::VerilogDesign::Trigger
• BUF : oagFpga::VerilogDesign::Instantiation
• buildNetlist() : oagFpga::RtlGraph
• Bundle() : oagFpga::VerilogDesign::Bundle
• BUNDLE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• bundle : YYSTYPE, oagFpga::VerilogDesign::Expression
• busMux() : oagFpga::RtlGraph
• busNet2Ai() : oagFpga::ModuleCompiler

- c -

• Case() : oagFpga::VerilogDesign::Case
• CASE : oagFpga::VerilogDesign::Statement
• cases : YYSTYPE, oagFpga::VerilogDesign::Statement
• CASEX : oagFpga::VerilogDesign::Statement
• CASEZ : oagFpga::VerilogDesign::Statement
• checkForExistenceOfDesign() : oagFpga::Synthesis
• choice_n : oagFpga::FpgaMapper
• choice_p : oagFpga::FpgaMapper
• chooseEquivalent() : oagFpga::AiModGraph
• clear() : oagFunc::SimOcc, oagFpga::SimMod
• clearExternalReferences() : oagFpga::AiModGraph
• clearKfeasibleCuts() : oagFpga::AiModGraph
• clock : oagFpga::RtlNode::RtlSeqNodeInfo
• compileBBNode() : oagFpga::ModuleCompiler
• compileFunctionalBBNode() : oagFpga::ModuleCompiler
• compileFunctionalMuxBBNode() : oagFpga::ModuleCompiler
• compileFunctionalOptBBNode() : oagFpga::ModuleCompiler
• compileFunctionalSeqBBNode() : oagFpga::ModuleCompiler
• compileModules() : oagFpga::ModuleCompiler
• compileOneModule() : oagFpga::ModuleCompiler
• condition : oagFpga::VerilogSynthesis::ConditionalLvalRef, oagFpga::VerilogDesign::Statement
• conditionalLval : oagFpga::VerilogSynthesis::LvalRef
• ConditionalLvalRef() : oagFpga::VerilogSynthesis::ConditionalLvalRef
• conditions : oagFpga::VerilogDesign::Case
• connectEquivalentNetsInGraph() : oagFpga::ModGraph, oagFpga::AiModGraph
• connections : oagFpga::VerilogDesign::Instantiation
• connectPort() : oagFpga::Synthesis
• CONST : oagFpga::VerilogDesign::Primary
• CONSTANT0 : oagFpga::RtlNode
• CONSTANT0_BBREF : oagFpga::RtlGraph
• CONSTANT1 : oagFpga::RtlNode
• CONSTANT1_BBREF : oagFpga::RtlGraph
• constantOne() : oagFpga::Synthesis, oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• constantZero() : oagFpga::Synthesis, oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• constantZeroEntry : oagFpga::FpgaMapper
• CONTROL : oagFpga::RtlNode
• convertAiModRefListToRefList() : oagFpga::AiModGraph
• convertModRefListToRefList() : oagFpga::ModGraph
• convertRefListToAiModRefList() : oagFpga::AiModGraph
• convertRefListToModRefList() : oagFpga::ModGraph
• convertRefVectorToAiModRefVector() : oagFpga::AiModGraph
• convertRefVectorToModRefVector() : oagFpga::ModGraph
• cost_n : oagFpga::FpgaMapper
• cost_p : oagFpga::FpgaMapper
• create() : oagFpga::Manager
• createBusNet() : oagFpga::Synthesis
• createLut() : oagFpga::MapperUtils
• createModule() : oagFpga::Synthesis
• createScalarNet() : oagFpga::Synthesis
• createSeq() : oagFpga::MapperUtils
• createTerm() : oagFpga::Synthesis
• currentLibrary : oagFpga::Synthesis
• currentManager : oagFpga::Synthesis, oagFpga::ModuleCompiler
• currentModule : oagFpga::Synthesis
• currentParams : oagFpga::VerilogSynthesis
• currentTraversalID : oagFpga::RtlGraph
• currentView : oagFpga::Synthesis
• currentVmodule : oagFpga::VerilogSynthesis
• curTrigger : oagFpga::VerilogSynthesis::ProceduralState
• Cut : oagFpga::OccGraph, oagFpga::AiModGraph
• cut_n : oagFpga::FpgaMapper
• cut_p : oagFpga::FpgaMapper
• CutSet : oagFpga::OccGraph, oagFpga::AiModGraph
• cutsPerNode : oagFpga::FpgaMapper

- d -

• D : oagFpga::RtlNode::RtlSeqNodeInfo
• data : oagFunc::SimOcc
• dataBBNodes : oagFpga::RtlGraph
• Declaration() : oagFpga::VerilogDesign::Declaration
• declaration : YYSTYPE
• declarations : YYSTYPE, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Module
• decls : YYSTYPE
• decrementExternalReferences() : oagFpga::AiModGraph
• dependencies : oagFpga::VerilogSynthesis::ProceduralState
• design : oagFpga::VerilogDesign::Module, oagFunc::SimOcc, oagFpga::SimMod, oagFpga::Manager
• destroy() : oagFpga::Manager
• detach() : oagFpga::AiModGraph
• DFF : oagFpga::RtlNode
• DIVIDE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode

- e -

• enumerateKfeasibleCuts() : oagFpga::AiModGraph
• EQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• equalTo() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• evaluateConstantExpression() : oagFpga::VerilogSynthesis
• evaluateExpression() : oagFpga::VerilogSynthesis
• evaluateLval() : oagFpga::VerilogSynthesis
• exhaustiveInputVectors : oagFpga::FpgaMapper
• Expression() : oagFpga::VerilogDesign::Expression
• expression : YYSTYPE
• expressions : YYSTYPE
• externalName : oagFpga::VerilogDesign::Port
• externalTerminalConnection : oagFpga::RtlNode

- f -

• failIfInDifferentModules() : oagFpga::ModGraph, oagFpga::AiModGraph
• fanin : oagFpga::RtlNode
• fanout : oagFpga::RtlNode
• findBusNet() : oagFpga::Synthesis
• findBusNetBit() : oagFpga::Synthesis
• findDriverOfEquivalentNets() : oagFpga::ModGraph, oagFpga::AiModGraph
• findModule() : oagFpga::Synthesis
• findNet() : oagFpga::Synthesis
• findScalarNet() : oagFpga::Synthesis
• finishedModules : oagFpga::VerilogSynthesis
• FpgaMapper : oagFpga::FpgaMapper, oagFpga::MapperUtils
• fullAdder() : oagFpga::ModuleCompiler
• Function() : oagFpga::VerilogDesign::Function
• FUNCTION_CALL : oagFpga::VerilogDesign::Primary
• functionAssignments : oagFpga::VerilogSynthesis::ProceduralState
• functionLvalBit : oagFpga::VerilogSynthesis::LvalRef
• functionLvalName : oagFpga::VerilogSynthesis::LvalRef
• functions : YYSTYPE, oagFpga::VerilogDesign::Module
• FunctionVariableAssignment() : oagFpga::VerilogSynthesis::FunctionVariableAssignment
• FuncType : oagFpga::RtlNode
• funcType : oagFpga::RtlNode
• funcTypeName : oagFpga::RtlNode

- g -

• gateCount : oagFpga::FpgaMapper
• generateRandomInputVectors() : oagFunc::SimOcc, oagFpga::SimMod
• generateRandomStateVectors() : oagFunc::SimOcc, oagFpga::SimMod
• get() : oagFpga::Manager
• getAiGraph() : oagFpga::Manager
• getAllConnections() : oagFpga::OccGraph, oagFpga::AiModGraph
• getAllNodes() : oagFpga::AiModGraph
• getAndLeft() : oagFpga::AiModGraph
• getAndRight() : oagFpga::AiModGraph
• getBBNodeNum() : oagFpga::RtlGraph
• getConstants() : oagFpga::OccGraph
• getContextualValue() : oagFpga::VerilogSynthesis
• getCumulativeAreaCost() : oagFpga::FpgaMapper
• getCumulativeDelayCost() : oagFpga::FpgaMapper
• getEquivalents() : oagFpga::AiModGraph
• getExternalTerminalConnection() : oagFpga::RtlGraph
• getFanin() : oagFpga::RtlGraph, oagFpga::ModGraph
• getFaninCone() : oagFpga::AiModGraph
• getFaninRoots() : oagFpga::AiModGraph
• getFanout() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getFanoutCone() : oagFpga::AiModGraph
• getFanoutOfEquivalentNodes() : oagFpga::AiModGraph
• getFanoutRoots() : oagFpga::AiModGraph
• getGraph() : oagFpga::ModGraph, oagFpga::AiModGraph
• getInputs() : oagFpga::OccGraph, oagFpga::AiModGraph
• getLocalStates() : oagFpga::OccGraph, oagFpga::AiModGraph
• getLut() : oagFpga::MapperUtils
• getModRef() : oagFpga::OccRef
• getNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
• getNetToBBAllEquivConnections() : oagFpga::OccGraph
• getNetToBBConnection() : oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::Manager
• getNextState() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getNode() : oagFpga::RtlGraph
• getNodeOptType() : oagFpga::RtlGraph, oagFpga::ModGraph
• getNodeSeqType() : oagFpga::RtlGraph, oagFpga::ModGraph
• getNodeType() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getNonInverted() : oagFpga::AiModGraph
• getNull() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getNumOutputBits() : oagFpga::RtlGraph, oagFpga::ModGraph
• getOutputBit() : oagFpga::RtlGraph
• getOutputs() : oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getParameterizedModuleName() : oagFpga::VerilogSynthesis
• getPrimaryBBID() : oagFpga::RtlGraph, oagFpga::ModGraph
• getSeq() : oagFpga::MapperUtils
• getSequentialData() : oagFpga::AiModGraph
• getSerializedSize() : oagFpga::Manager
• getStates() : oagFpga::OccGraph
• getTerminalDriver() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getTransitiveFanin() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getTransitiveFanin_recursive() : oagFpga::RtlGraph
• getTransitiveFanout() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• getTransitiveFanout_recursive() : oagFpga::RtlGraph
• getUserData() : oagFpga::AiModGraph
• getVector() : oagFunc::SimOcc, oagFpga::SimMod
• GREATER_THAN : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• GREATER_THAN_EQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• greaterThan() : oagFpga::Synthesis
• greaterThanEqual() : oagFpga::Synthesis

- h -

• hasCombinationalCycle() : oagFpga::RtlGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• hasCombinationalCycle_recursive() : oagFpga::RtlGraph
• hasFanout() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• hasManager() : oagFpga::Manager

- i -

• identifyControls() : oagFpga::MapperUtils
• IF : oagFpga::VerilogDesign::Statement
• IF_ELSE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• ifc : oagFpga::VerilogDesign::Statement
• ifFalse : oagFpga::VerilogDesign::Statement
• ifTrue : oagFpga::VerilogDesign::Statement
• implementAll() : oagFpga::FpgaMapper
• implementNode() : oagFpga::FpgaMapper
• implementSeqNode() : oagFpga::FpgaMapper
• in : oagFpga::RtlNode::RtlMuxNodeInfo
• incrementExternalReferences() : oagFpga::AiModGraph
• initialBlocks : YYSTYPE, oagFpga::VerilogDesign::Module
• initializeIncremental() : oagFunc::SimOcc, oagFpga::SimMod
• initializeSimulation() : oagFpga::FpgaMapper
• INOUT : oagFpga::VerilogDesign::Declaration
• INPUT : oagFpga::VerilogDesign::Declaration
• instantiateModule() : oagFpga::Synthesis
• Instantiation() : oagFpga::VerilogDesign::Instantiation
• instantiation : YYSTYPE
• instantiations : YYSTYPE, oagFpga::VerilogDesign::Module
• internalName : oagFpga::VerilogDesign::Port
• intValue : oagFpga::VerilogDesign::Primary, oagFpga::Synthesis::ConstantValue
• isAnd() : oagFpga::AiModGraph
• isAsynchronousSignal() : oagFpga::VerilogSynthesis
• isConstantExpression() : oagFpga::VerilogSynthesis
• isDefault : oagFpga::VerilogDesign::Case
• isFunction : oagFpga::VerilogSynthesis::ProceduralState
• isFunctional() : oagFpga::RtlGraph, oagFpga::ModGraph
• isInverted() : oagFpga::AiModGraph
• ISNT_PRIMITIVE : oagFpga::VerilogDesign::Instantiation
• isNull() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• isRegister : oagFpga::VerilogSynthesis::ProceduralState
• isSequential() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• isStructural() : oagFpga::Manager
• isTerminal() : oagFpga::RtlGraph, oagFpga::OccGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• isVisited() : oagFpga::RtlGraph

- l -

• lastManagerDesign : oagFpga::Manager
• lastManagerObject : oagFpga::Manager
• LATCH : oagFpga::RtlNode
• latch() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• leafLibs : oagFpga::Synthesis
• leafViews : oagFpga::Synthesis
• LEFT_SHIFT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• leftShift() : oagFpga::Synthesis
• LESS_THAN : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LESS_THAN_EQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• lessThan() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• lessThanEqual() : oagFpga::Synthesis
• LOGICAL_AND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LOGICAL_NOT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• LOGICAL_OR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• logicAnd() : oagFpga::Synthesis
• logicNot() : oagFpga::Synthesis
• logicOr() : oagFpga::Synthesis
• lower : oagFpga::Synthesis::Bounds
• lutArea : oagFpga::MapperUtils
• lutDelay : oagFpga::MapperUtils
• lutGate : oagFpga::MapperUtils
• lutInputs : oagFpga::MapperUtils
• lutOutput : oagFpga::MapperUtils
• lval : oagFpga::VerilogSynthesis::ConditionalLvalRef, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Assignment
• LVAL_CONDITIONAL : oagFpga::VerilogSynthesis
• LVAL_FUNCTION : oagFpga::VerilogSynthesis
• LVAL_UNCONDITIONAL : oagFpga::VerilogSynthesis
• LVAL_UNKNOWN : oagFpga::VerilogSynthesis
• LvalRef() : oagFpga::VerilogSynthesis::LvalRef
• LvalRefBus : oagFpga::VerilogSynthesis
• LvalType : oagFpga::VerilogSynthesis

- m -

• Manager : oagFpga::Manager, oagFpga::RtlGraph
• mapped : oagFpga::FpgaMapper
• MapperUtils : oagFpga::MapperUtils, oagFpga::Synthesis
• mapUtils : oagFpga::FpgaMapper
• markVisited() : oagFpga::RtlGraph
• members : oagFpga::VerilogDesign::Bundle
• mergeEquivalentNets() : oagFpga::MapperUtils
• ModGraph : oagFpga::Manager
• ModRef() : oagFpga::ModRef
• module : YYSTYPE, oagFpga::ModRef, oagFpga::AiModRef
• Module() : oagFpga::VerilogDesign::Module
• ModuleCompiler : oagFpga::RtlGraph, oagFpga::Manager
• modules : oagFpga::VerilogDesign
• MODULO : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• multiBitConstant() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• MULTIPLY : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• MultiRef() : oagFpga::MultiRef
• mux() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• muxInfo : oagFpga::RtlNode

- n -

• name : oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::PortConnection, oagFpga::VerilogDesign::Instantiation, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Declaration, oagFpga::VerilogDesign::Module
• NAME_LENGTH_LIMIT : oagFpga::Synthesis
• nameSpace : oagFpga::Synthesis
• NAND : oagFpga::VerilogDesign::Instantiation
• nandOf() : oagFpga::Synthesis
• negAsyncResets : oagFpga::MapperUtils
• NEGATE : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• negative : YYSTYPE, oagFpga::VerilogDesign::Primary
• negClocks : oagFpga::MapperUtils
• NEGEDGE : oagFpga::VerilogDesign::Trigger, oagFpga::MapperUtils, oagFpga::FpgaMapper
• negTriggers : oagFpga::VerilogSynthesis::ProceduralState
• NET : oagFpga::VerilogDesign::Primary
• net : oagFpga::VerilogDesign::Trigger, oagFpga::MultiRef
• newAnd() : oagFpga::AiModGraph
• newNode() : oagFpga::RtlGraph
• newSequential() : oagFpga::AiModGraph
• newTerminal() : oagFpga::RtlGraph, oagFpga::AiModGraph
• newTraversalID() : oagFpga::RtlGraph
• nextCycle() : oagFunc::SimOcc, oagFpga::SimMod
• NONBLOCKING_ASSIGNMENT : oagFpga::VerilogDesign::Statement
• nonblockingAssignments : oagFpga::VerilogSynthesis::ProceduralState
• nonClockTriggers : oagFpga::VerilogSynthesis::ProceduralState
• NOP : oagFpga::VerilogDesign::Statement
• NOR : oagFpga::VerilogDesign::Instantiation
• normalTriggers : oagFpga::VerilogSynthesis::ProceduralState
• norOf() : oagFpga::Synthesis
• NOT : oagFpga::VerilogDesign::Instantiation
• notEntry : oagFpga::FpgaMapper
• NOTEQUAL : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• notEqualTo() : oagFpga::Synthesis
• notOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler, oagFpga::AiModGraph
• NULL_BBREF : oagFpga::RtlGraph
• NULL_FUNC : oagFpga::RtlNode
• number : YYSTYPE, oagFpga::VerilogDesign::Primary
• numOutputBits : oagFpga::RtlNode

- o -

• Observer() : oagFpga::Observer
• OccGraph : oagFpga::Manager
• OccRef() : oagFpga::OccRef
• occurrence : oagFpga::OccRef
• onFirstOpen() : oagFpga::Observer
• onPostSave() : oagFpga::Observer
• onPreSave() : oagFpga::Observer
• onPurge() : oagFpga::Observer
• op1 : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode::RtlOptNodeInfo
• op2 : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode::RtlOptNodeInfo
• op3 : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode::RtlOptNodeInfo
• OPERATOR : oagFpga::RtlNode
• Operator : oagFpga::VerilogDesign::Expression
• operator!=() : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
• operator<() : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
• operator=() : oagFpga::MultiRef
• operator==() : oagFpga::OccRef, oagFpga::MultiRef, oagFpga::ModRef, oagFpga::AiModRef
• optInfo : oagFpga::RtlNode
• optType : oagFpga::RtlNode
• OptType : oagFpga::RtlNode
• optTypeName : oagFpga::RtlNode
• OR : oagFpga::VerilogDesign::Instantiation
• orOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• OUTPUT : oagFpga::VerilogDesign::Declaration
• overwriteStructure : oagFpga::Synthesis

- p -

• PARAMETER : oagFpga::VerilogDesign::Declaration
• parameterOverrides : YYSTYPE, oagFpga::VerilogDesign::Module
• parameters : oagFpga::VerilogDesign::Instantiation, oagFpga::VerilogDesign::Module
• ParameterValues : oagFpga::VerilogSynthesis
• PortConnection() : oagFpga::VerilogDesign::PortConnection
• portConnection : YYSTYPE
• portConnections : YYSTYPE
• ports : YYSTYPE, oagFpga::VerilogDesign::Module
• posAsyncResets : oagFpga::MapperUtils
• posClocks : oagFpga::MapperUtils
• POSEDGE : oagFpga::VerilogDesign::Trigger, oagFpga::MapperUtils, oagFpga::FpgaMapper
• position : oagFpga::VerilogDesign::PortConnection, oagFpga::VerilogDesign::Port
• posTriggers : oagFpga::VerilogSynthesis::ProceduralState
• prepareNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
• prepareNetToBBConnection() : oagFpga::ModGraph, oagFpga::Manager
• primaries : YYSTYPE
• Primary() : oagFpga::VerilogDesign::Primary
• primary : YYSTYPE, oagFpga::VerilogDesign::Expression
• PRIMARY : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• primitive : oagFpga::VerilogDesign::Instantiation
• PrimitiveType : oagFpga::VerilogDesign::Instantiation
• print() : oagFpga::RtlGraph, oagFpga::OccRef, oagFpga::ModRef, oagFpga::Manager, oagFpga::AiModRef, oagFpga::AiModGraph
• printBitNetName() : oagFpga::VerilogSynthesis
• printGateUsage() : oagFpga::MapperUtils
• printName() : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
• ProceduralState() : oagFpga::VerilogSynthesis::ProceduralState
• PSTATE_ASYNC : oagFpga::VerilogSynthesis::ProceduralState
• PSTATE_SYNC : oagFpga::VerilogSynthesis::ProceduralState
• pStateType : oagFpga::VerilogSynthesis::ProceduralState
• PStateType : oagFpga::VerilogSynthesis::ProceduralState

- r -

• randomVector() : oagFunc::SimOcc, oagFpga::SimMod
• range : oagFpga::VerilogDesign::Primary
• REDUCTION_AND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_NAND : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_NOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_OR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_XNOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• REDUCTION_XOR : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• reductionAnd() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• reductionNand() : oagFpga::Synthesis
• reductionNor() : oagFpga::Synthesis
• reductionOr() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• reductionXnor() : oagFpga::Synthesis
• reductionXor() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• ref : oagFpga::OccRef, oagFpga::ModRef, oagFpga::AiModRef
• REG : oagFpga::VerilogDesign::Declaration
• removeAsyncResetsFromLogic() : oagFpga::MapperUtils
• removeDanglingNets() : oagFpga::MapperUtils
• removeEquivalences() : oagFpga::AiModGraph
• removeFromFanout() : oagFpga::RtlGraph
• removeNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
• removeNetToBBConnection() : oagFpga::ModGraph
• replication : oagFpga::VerilogDesign::Bundle
• resubstitute() : oagFpga::AiModGraph
• RIGHT_SHIFT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• RtlGraph : oagFpga::RtlGraph, oagFpga::RtlNode
• RtlNode() : oagFpga::RtlNode
• RtlSeqNodeInfo() : oagFpga::RtlNode::RtlSeqNodeInfo
• runFull() : oagFunc::SimOcc, oagFpga::SimMod
• runIncremental() : oagFunc::SimOcc, oagFpga::SimMod
• runOne() : oagFpga::SimMod
• rval : oagFpga::VerilogDesign::Statement

- s -

• scalarNet2Ai() : oagFpga::ModuleCompiler
• sel : oagFpga::RtlNode::RtlMuxNodeInfo
• self : oagFpga::RtlNode
• SEQ : oagFpga::RtlNode
• seq() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• seqArea : oagFpga::MapperUtils
• seqClock : oagFpga::MapperUtils
• seqClockTrigger : oagFpga::MapperUtils
• seqCount : oagFpga::FpgaMapper
• seqDelay : oagFpga::MapperUtils
• seqGate : oagFpga::MapperUtils
• seqInfo : oagFpga::RtlNode
• seqInput : oagFpga::MapperUtils
• seqOutput : oagFpga::MapperUtils
• seqPreset : oagFpga::MapperUtils
• seqPresetTrigger : oagFpga::MapperUtils
• seqReset : oagFpga::MapperUtils
• seqResetTrigger : oagFpga::MapperUtils
• seqType : oagFpga::RtlNode
• SeqType : oagFpga::RtlNode
• seqTypeName : oagFpga::RtlNode
• serialize() : oagFpga::Manager
• setAndLeft() : oagFpga::AiModGraph
• setAndRight() : oagFpga::AiModGraph
• setAreaCosts() : oagFpga::FpgaMapper
• setDelayCosts() : oagFpga::FpgaMapper
• setEquivalent() : oagFpga::AiModGraph
• setExternalTerminalConnection() : oagFpga::RtlGraph
• setLibrary() : oagFpga::Synthesis
• setLut() : oagFpga::MapperUtils
• setNetToAiConnection() : oagFpga::Manager, oagFpga::AiModGraph
• setNetToBBConnection() : oagFpga::ModGraph, oagFpga::Manager
• setNextState() : oagFpga::AiModGraph
• setOverwriteStructure() : oagFpga::Synthesis
• setSeq() : oagFpga::MapperUtils
• setTerminalDriver() : oagFpga::RtlGraph, oagFpga::ModGraph, oagFpga::AiModGraph
• setUserData() : oagFpga::AiModGraph
• setVector() : oagFunc::SimOcc, oagFpga::SimMod
• setView() : oagFpga::Synthesis
• SIM_USER_DATA_INDEX : oagFpga::SimMod
• SimMod : oagFpga::SimMod, oagFpga::AiModGraph
• SimOcc() : oagFunc::SimOcc
• simulate() : oagFpga::FpgaMapper
• SimVec : oagFunc::SimOcc, oagFpga::SimMod
• start : oagFpga::VerilogSynthesis::FunctionVariableAssignment, oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Declaration
• start2D : oagFpga::VerilogDesign::Declaration
• Statement() : oagFpga::VerilogDesign::Statement
• statement : YYSTYPE
• statements : YYSTYPE
• stop : oagFpga::VerilogSynthesis::FunctionVariableAssignment, oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Function, oagFpga::VerilogDesign::Declaration
• stop2D : oagFpga::VerilogDesign::Declaration
• str : YYSTYPE
• SUBTRACT : oagFpga::VerilogDesign::Expression, oagFpga::RtlNode
• SUPPLY0 : oagFpga::VerilogDesign::Declaration
• SUPPLY1 : oagFpga::VerilogDesign::Declaration
• Synthesis : oagFpga::Manager
• synthesize() : oagFpga::VerilogSynthesis
• synthesizeBehavioral() : oagFpga::VerilogSynthesis
• synthesizeBlock() : oagFpga::VerilogSynthesis
• synthesizeBlockingassignment() : oagFpga::VerilogSynthesis
• synthesizeCase() : oagFpga::VerilogSynthesis
• synthesizeCaseEasy() : oagFpga::VerilogSynthesis
• synthesizeIf() : oagFpga::VerilogSynthesis
• synthesizeModule() : oagFpga::VerilogSynthesis
• synthesizeModuleAssigns() : oagFpga::VerilogSynthesis
• synthesizeModuleFunc() : oagFpga::VerilogSynthesis
• synthesizeModuleInsts() : oagFpga::VerilogSynthesis
• synthesizeModuleNets() : oagFpga::VerilogSynthesis
• synthesizeModuleTerms() : oagFpga::VerilogSynthesis
• synthesizeNonblockingassignment() : oagFpga::VerilogSynthesis

- t -

• techmapArea() : oagFpga::FpgaMapper
• techmapDelay() : oagFpga::FpgaMapper
• TERMINAL : oagFpga::RtlNode
• testEquivalence() : oagFpga::AiModGraph
• toBeSimulated : oagFunc::SimOcc, oagFpga::SimMod
• totalArea : oagFpga::FpgaMapper
• totalDelay : oagFpga::FpgaMapper
• traversalID : oagFpga::RtlNode
• TRI : oagFpga::VerilogDesign::Declaration
• TRI0 : oagFpga::VerilogDesign::Declaration
• TRI1 : oagFpga::VerilogDesign::Declaration
• TRIAND : oagFpga::VerilogDesign::Declaration
• Trigger() : oagFpga::VerilogDesign::Trigger
• trigger : YYSTYPE
• triggers : YYSTYPE, oagFpga::VerilogDesign::AlwaysBlock
• TriggerType : oagFpga::MapperUtils, oagFpga::FpgaMapper
• TRIOR : oagFpga::VerilogDesign::Declaration
• twoDimRegisters : oagFpga::VerilogSynthesis
• type : oagFpga::VerilogSynthesis::LvalRef, oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Expression, oagFpga::VerilogDesign::Instantiation, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Trigger, oagFpga::VerilogDesign::Declaration, oagFpga::MultiRef
• Type : oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Statement, oagFpga::VerilogDesign::Trigger, oagFpga::VerilogDesign::Declaration

- u -

• unaryBusInputOutputOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
• unaryBusOpt() : oagFpga::Synthesis, oagFpga::RtlGraph
• unaryOpt() : oagFpga::RtlGraph
• unconditionalLval : oagFpga::VerilogSynthesis::LvalRef
• UNKNOWN : oagFpga::VerilogDesign::Primary, oagFpga::VerilogDesign::Expression, oagFpga::VerilogDesign::Trigger, oagFpga::VerilogDesign::Declaration, oagFpga::RtlNode
• unmarkVisited() : oagFpga::RtlGraph
• unserialize() : oagFpga::Manager
• upper : oagFpga::Synthesis::Bounds

- v -

• value : YYSTYPE, oagFpga::VerilogDesign::PortConnection, oagFpga::VerilogDesign::Assignment, oagFpga::VerilogDesign::Declaration

- w -

• WIRE : oagFpga::VerilogDesign::Declaration
• WIREAND : oagFpga::VerilogDesign::Declaration
• WIREOR : oagFpga::VerilogDesign::Declaration

- x -

• xMask : oagFpga::VerilogDesign::Primary
• xmask : YYSTYPE
• XNOR : oagFpga::VerilogDesign::Instantiation
• xnorOf() : oagFpga::Synthesis
• XOR : oagFpga::VerilogDesign::Instantiation
• xorOf() : oagFpga::Synthesis, oagFpga::ModuleCompiler

- z -

• zeroExpand() : oagFpga::Synthesis, oagFpga::ModuleCompiler
• zmask : YYSTYPE
• zMask : oagFpga::VerilogDesign::Primary

- ~ -

• ~AlwaysBlock() : oagFpga::VerilogDesign::AlwaysBlock
• ~Assignment() : oagFpga::VerilogDesign::Assignment
• ~Bundle() : oagFpga::VerilogDesign::Bundle
• ~Case() : oagFpga::VerilogDesign::Case
• ~Declaration() : oagFpga::VerilogDesign::Declaration
• ~Expression() : oagFpga::VerilogDesign::Expression
• ~Function() : oagFpga::VerilogDesign::Function
• ~Instantiation() : oagFpga::VerilogDesign::Instantiation
• ~Manager() : oagFpga::Manager
• ~Module() : oagFpga::VerilogDesign::Module
• ~Port() : oagFpga::VerilogDesign::Port
• ~PortConnection() : oagFpga::VerilogDesign::PortConnection
• ~Primary() : oagFpga::VerilogDesign::Primary
• ~RtlGraph() : oagFpga::RtlGraph
• ~RtlNode() : oagFpga::RtlNode
• ~Statement() : oagFpga::VerilogDesign::Statement
• ~Trigger() : oagFpga::VerilogDesign::Trigger
• ~VerilogDesign() : oagFpga::VerilogDesign

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